AMD Zen: More Details Leaked Based on Patches and Patents
More information about AMD Zen core’s IP blocks has emerged online thanks to a new series of patches recently posted on the Linux kernel mailing list by an AMD employee. The latest round of patches even mentions a “ZP” target, which most likely refers to Zeppelin.
First spotted by The New Citavia Blog, the patches reveal new additions to Machine Check Architecture (MCA); AMD’s implementation in the Linux EDAC kernel module, which is responsible for hardware error detection and correction. Most notably, new details confirm the “GMI link” mentioned on an already leaked slide, which reported a bandwidth of 25 GB/s per link.
Below are some of the key changes as summarized by Dresdenboy;
- uOp Cache has been added based on the new patch.
- FMUL/FADD for FMAC pairing removed, based on some corrections of the znver1 pipeline description.
- 4x parallel Page Table Walkers added, based on US20150121046.
- 128b FP datapaths (also to/from the L1 D$) based on “direct” decode for 128b wide SIMD and “double” decode for 256b AVX/AVX2 instructions.
- 32kB L1 I$ has been mentioned in some patents. With enough ways, a fast L2$ and a uOp cache this should be enough, I think.
- Issue port descriptions and more data paths added.
- 2R1W and 4 cycle load-to-use-latency added for the L1 D$ based on info found on a LinkedIn profile and the given cylce differences in the znver1 pipeline description.
- Stack Cache speculatively added based on patents and some interesting papers. This doesn’t help so much with performance, but a lot with power efficiency.
Dresdenboy has also updated the Zen core diagram based on these new informations and some related patents and papers:
AMD Zen To Have 32 Cores per Socket
Recently, a CERN engineer revealed that AMD’s upcoming x86 processors based on Zen would arrive at some point in a 32-core implementation. To achieve this core design, he said AMD would implement a pair of 16-core complexes on a single die, with a high speed interconnect between them — that would presumably reduce or be void of bottlenecks.
Besides the core count, another exciting feature of Zen is Symmetrical Multi-threading (SMT) design, which will bring same performance gains as Intel’s Hyper Threading technology.
AMD Zen to Bring Greater than 40% IPC Increase
Built on a 14nm process, AMD Zen is also rumored to bring greater than 40% improvement in instructions per clock (IPC) over their current lineup. This dramatic increase in IPC, combined with higher core count, could offer very potent and compelling solutions in the data center applications.
Moreover, AMD believes the new architecture would mark the company’s “re-entry” into the high-performance desktop market as it will bring instruction set parity with competitor’s and a reworked and more balanced design.
Last but not least, Zen will come with a unified AM-4 socket bringing support for DDR4 memory and other technologies.
As for availability, the first Zen-based chips, code-named Summit Ridge, will debut on high-end desktops at the end of this year. Later, the chips will make their way to servers in early 2017.
Gohar is the lead editor at TechFrag. He has a wide range of interests when it comes to tech but he's currently spending a big chunk of his time writing about privacy, cyber security, and anything policy related.