AMD Summit Ridge CPU Die Leaked – Four Zen Based cores, 16MB of L3 cache, and a DDR4 interface
It seems like AMD has accidentally outed a rendering of their upcoming high-end Summit Ridge wafer at its May 12th shareholders meeting, reports SemiAccurate.
Summit Ridge is expected to be the first chip from AMD that is based on the company’s next generation Zen CPU architecture. Rumors suggest that this is the high-end desktop (HEDT) product which could launch in Q4 of this year.
Looking at the just-leaked CPU dieshot, Summit Ridge appears to feature two quad core modules or groupings and a separate memory interface for each grouping. This lines up nicely with previous rumors which suggested that Zen-cored server chips will range in core count from 16 to 32 cores–with the architecture scaled by fours. However, we still don’t know how AMD plans to scale from this apparently 8 core die to 16 and 32 cores.
Dresdenboy of New Citavia Blog also posted his interpretation of this Summit Ridge wafer image. He points out four cores, an L3 cache in the center, and a dual-channel DDR4 memory controller on top all appear to be part of a single Zen module. Further, the processor die also hints at an integrated south bridge, as AMD promised for the Summit Ridge.
The upcoming Zen based chip could have 512 KB of L2 cache per core, and 16 MB of shared L3 cache split between two blocks of four CPU cores, each.
If previous reports are to be believed, the 8-core Summit Ridge CPU dies have already taped out in January. The products are rumored to feature a 95W TDP, and will be released on the new AM4 socket. Some reports also suggest that AMD’s HEDT processors will integrate the new Global Memory Interconnect (GMI) bus that provides up to 100 GB/s path between two sockets using four links.
Built using the new 14nm FinFET process technology, AMD Summit Ridge is expected to be very power efficient and be on par with Intel “Broadwell-E” processors.
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