Intel Says Good Bye To Tick-Tock Strategy As It Welcomes a 3-Step PAO Model
Intel adopted their Tick-Tock strategy back in 2006, and since then, the chip maker has been releasing new processors following the same model. Two generations are based on a single processing node; the Tick moves to a new processing node, improves efficiency and brings minor changes to architecture, while the Tock makes some major architectural changes to the CPU.
Based on the fundamentals of Moore’s Law, the Tick-Tock strategy has served Intel well in the past, but during the recent years the semiconductor giant started experiencing difficulties as it tried to continue making its manufacturing technology smaller and smaller. So it comes as no surprise that Intel is now devising a completely new strategy called “Process, Architecture and Optimization.”
In its recent 10-K filing, Intel stated the following:
As part of our R&D efforts, we plan to introduce a new Intel Core microarchitecture for desktops, notebooks (including Ultrabook devices and 2 in 1 systems), and Intel Xeon processors on a regular cadence. We expect to lengthen the amount of time we will utilize our 14nm and our next generation 10nm process technologies, further optimizing our products and process technologies while meeting the yearly market cadence for product introductions.
Under the new PAO strategy, the first year marks the arrival of a new process node, which is based on a known architecture. It is then followed by a new architecture, while in the third year, Intel would be optimizing both the process and architecture for the final release on that process.
Take example of the 14nm process. Following the latest PAO model, Broadwell arrived in 2014 (Process), followed by the new Skylake architecture in 2015 (Architecture), and then Kaby Lake, which is an optimized Skylake architecture still on 14nm, is set to launch this year (Optimization).
Intel said it’s planning on introducing multiple product families at future nodes, with advances that would “result in a significant reduction in transistor leakage, lower active power, and an increase in transistor density to enable more smaller form factors.”