Stanford Engineers Create Skyscraper Computer System To Boost Performance By Factor Of Thousand
One of the major reasons for delay in processing times and energy waste in modern computer systems is the single-story ‘suburban’ layout in which processor, RAM and other components are placed. However, an ongoing research at Stanford seems to have altered this layout and thus created a system that boosts performance by factor of a thousand.
Stanford University engineers including Associate Professor Subhasish Mitra and Professor Philip Wong have been working with some other institute to make this skyscraper-style ‘high-rise’ chip design to revolutionize computer architecture. The new system was showcased in Rebooting Computing, a special issue of the IEEE Computer journal and is known as Nano-Engineered Computing Systems Technology or simply N3XT.
N3XT will break data bottlenecks by integrating processors and memory like floors in a skyscraper and by connecting these components with millions of “vias,” which play the role of tiny electronic elevators. The N3XT high-rise approach will move more data, much faster, using far less energy, than would be possible using low-rise circuits. The fact that it is based on nano-materials more advanced than silicon only helps its computing performance.
Mitra and Wong have already demonstrated a working prototype of a high-rise chip. At the International Electron Devices Meeting in December 2014, they unveiled a four-layered chip made up of two layers of RRAM memory sandwiched between two layers of CNTs.
In their N3XT paper, they ran simulations showing how their high-rise approach was a thousand times more efficient in carrying out many important and highly demanding industrial software applications.
“When you combine higher speed with lower energy use, N3XT systems outperform conventional approaches by a factor of a thousand,” Wong said.
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