More Details About AMD Bristol Ridge APU Family and SKUs Leaked
A few days ago, it was rumored that AMD might be readying for an early launch of their AM4 platform since the company has already finalized and taped out Zen based Summit Ridge processors. Now, a new report has surfaced claiming that the US-based chip maker has plans to launch their entire Bristol Ridge family first for the AM4 and FP4 platforms.
The latest information comes from Benchlife who has leaked several slides detailing the upcoming APU families for the AM4 and FP4 platforms. According to the slides, the Bristol Ridge APU family is known as the AMD Family 15h Models 65h-6Fh (BKDG and Electrical Datasheet) that will replace the Carrizo APUs on mobile front and Godavari APUs on desktop front.
The Bristol Ridge AM4 APU family will pack 8 SKUs, out of which seven SKUs are based on a quad core design while one chip retains a dual core design. The AM4 APUs will be utilize a new branding scheme, most probably A-Series 9000, with clock speeds ranging from 2.5 to 3.6 GHz base and 2.8 to 4.0 GHz boost clocks.
The APUs are expected to launch in the first half of 2016 which makes sense since users will have a range of AM4 motherboard options for their new processors. Based on the latest chip architectures from AMD, the new CPUs integrate a wide I/O capabilities, DDR4 memory support and a broad range of updates over the aged AM3+ platform.
The FP4 will be the first mobile platform from AMD that supports DDR4 memory standard. The FP4 platform itself will be compatible with current generation Carrizo and next generation Bristol Ridge and Stoney Ridge APUs.
As for the desktop part, there will be AM4 platform which includes the x86 Excavator based Bristol Ridge APUs for mainstream desktop systems and the Zen based Summit Ridge processors for enthusiast grade desktop systems.
The pricing is expected to remain the same as it is for their current desktop APUs which cost under the $200 range. In addition, AMD might launch a few budget options for Bristol Ridge APUs.